Preliminary Analysis of Impedance Control of PCB
Published on 1/17/2019 2:11:47 PM
Description
<p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Without </span><a href="https://www.allpcb.com/characteristic_impedance.html" target="_blank"><span style="font-family:"font-size:18px;">impedance control</span></a><span style="font-family:"font-size:18px;">, considerable signal reflections and signal distortions are caused, resulting in design failure. Common signals, such as PCI bus, PCI-E bus, USB, Ethernet, DDR memory, LVDS signals, etc., require impedance control. Impedance control ultimately needs to be realized through PCB design.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">It also puts higher requirements on the PCB board process. After communication with the PCB factory and combined with the use of EDA software, the impedance of the trace is controlled according to the signal integrity requirements. Different routing methods can be calculated to obtain the corresponding </span><span style="font-family:"font-size:18px;">impedance </span><span style="font-family:"font-size:18px;">values.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l0 level1 lfo1;"><span style="font-family:"font-size:18px;">1. </span><strong><span style="font-family:"font-size:18px;">Microstrip Line</span></strong> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">It consists of a strip conductor and a ground plane with a dielectric in between. If the dielectric constant of the dielectric, the width of the line, and its distance from the ground plane are controllable, its characteristic impedance is also controllable and its accuracy will be within ±5%.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-align:center;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><img width="363" height="152" src="https://file.allpcb.com/bbs/19/01/17/140631153.png"/><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="margin-left:0.0000pt;mso-para-margin-left:0.0000gd;text-indent:0.0000pt;mso-char-indent-count:0.0000;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l0 level1 lfo1;"><span style="font-family:"font-size:18px;">2. </span><strong><span style="font-family:"font-size:18px;">Stripline</span></strong> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">A stripline is a strip of copper placed between the dielectric layers between two layers of conductive planes. If the thickness and width of the line, the dielectric constant of the medium, and the distance between the two ground planes are all controllable, the characteristic impedance of the line is also controllable with an accuracy of 10%.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">In order to perform good impedance control on the PCB, we must first understand the structure of the PCB:</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Generally speaking, the multi-layer board is made by laminating and laminating the core board and the prepreg. The core board is a hard, special thickness, two-bread copper sheet, which is the basic material for the printed board.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">The prepreg constitutes a so-called wetting layer which acts to bond the core sheet, although it also has a certain initial thickness, but its thickness will change somewhat during the pressing process.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Usually the outermost two dielectric layers of the multilayer board are both wetting layers, and a separate copper foil layer is used as the outer copper foil on the outside of the two layers. The original thickness specifications of the outer copper foil and the inner copper foil are generally 0.5OZ, 1OZ, 2OZ (1OZ is about 35um or 1.4mil), but after a series of surface treatments, the final thickness of the outer copper foil is generally Will increase by nearly 1OZ.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">The inner <a href="https://www.allpcb.com/sns/top-10-defects-of-pcb-board-design-proce_26248.html" target="_self" title="Top 10 Defects of PCB Board Design Process">copper foil</a> is the copper coated on both sides of the core board, and the final thickness is very small from the original thickness, but due to etching, a few um is generally reduced.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">The outermost layer of the multilayer board is a </span><a href="https://www.allpcb.com/soldermask/" target="_blank"><span style="font-family:"font-size:18px;">solder mask</span></a><span style="font-family:"font-size:18px;">, which is what we often call "green oil". Of course, it can also be yellow or other colors. The thickness of the solder mask is generally not easy to determine accurately. The area without copper foil on the surface is slightly thicker than the area with copper foil.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">However, because of the lack of thickness of copper foil, the copper foil is still more prominent when we use You can feel it when you touch the surface of the printed board with your fingers.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">When making a printed board of a certain thickness, on the one hand, it is required to reasonably select the parameters of various materials. On the other hand, the final forming thickness of the prepreg is also smaller than the initial thickness.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="margin-left:0.0000pt;mso-para-margin-left:0.0000gd;text-indent:0.0000pt;mso-char-indent-count:0.0000;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l0 level1 lfo1;"><span style="font-family:"font-size:18px;">3. </span><strong><span style="font-family:"font-size:18px;">PCB Parameters</span></strong> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Different PCB manufacturers, PCB parameters will have subtle differences, through the communication with the circuit board factory technical support, get some parameters of the plant.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Surface copper foil: There are three types of surface copper foil materials that can be used: 12um, 18um and 35um. The final thickness after processing is approximately 44um, 50um and 67um.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Core board: Our commonly used plates are S1141A, standard FR-4, two bread copper, and the available specifications can be determined by the manufacturer.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Prepreg:The specifications (original thickness) are 7628 (0.185mm), 2116 (0.105mm), 1080 (0.075mm), and 3313 (0.095mm). The thickness after the actual pressing is usually 10-15um smaller than the original value. The same wetting layer can use up to three prepregs, and the thickness of the three prepregs cannot be the same.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">At least one prepreg can be used, but some manufacturers require at least two. If the thickness of the prepreg is insufficient, the copper foil on both sides of the core can be etched away and then adhered on both sides with a prepreg, so that a thicker wetting layer can be achieved.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Solder mask: The thickness of the solder mask on the copper foil is C2≈8-10um, and the thickness of the solder mask on the surface without copper foil is different according to the thickness of the surface copper. When the surface copper thickness is 45um, C1≈13-15um When the surface copper thickness is 70um, C1≈17-18um.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Wire cross section: We would think that the cross section of the wire is a rectangle, but it is actually a trapezoid. Taking the TOP layer as an example, when the thickness of the copper foil is 1 OZ, the upper bottom side of the trapezoid is 1 mil shorter than the lower bottom side.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">For example, if the line width is 5 MIL, then the upper bottom edge is about 4 mils and the lower bottom edge is 5 mil. The difference between the upper and lower hem is related to the copper thickness. The following table shows the relationship between the trapezoidal bottom and bottom in different situations.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-align:center;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><img width="592" height="152" src="https://file.allpcb.com/bbs/19/01/17/140645304.png"/><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Dielectric constant: The dielectric constant of the prepreg is related to the thickness. The dielectric constant of the sheet is related to the resin material used. The dielectric constant of the FR4 sheet is 4.2-4.7 and decreases with increasing frequency.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Dielectric loss factor: The energy consumed by a dielectric material under the action of an alternating electric field is called dielectric loss, and is usually expressed by the dielectric loss factor tan δ. A typical value for the S1141A is 0.015.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">The minimum line width and line spacing to ensure processing: 4mil / 4mil.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Introduction to the tool for impedance calculation:Once we understand the structure of the multi-layer board and master the required parameters, the impedance can be calculated by the EDA software. You can use Allegro to calculate, but here is another tool, Polar SI9000, which is a good tool for calculating characteristic impedance, which is now used by many PCB manufacturers.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Whether it is a differential line or a single-ended line, when calculating the characteristic impedance of the inner signal, you will find that there is only a slight difference between the calculation result of Polar SI9000 and Allegro, which is related to some details of the processing, such as the cross section of the wire. shape.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">But if you are calculating the characteristic impedance of the surface signal, I suggest you choose the Coated model instead of the Surface model, because the model considers the existence of the solder mask, so the result will be more accurate. The following figure is a partial screenshot of the differential line impedance of the lower layer in the case of considering the solder mask with the Polar SI9000:</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-align:center;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><img width="240" height="152" src="https://file.allpcb.com/bbs/19/01/17/140656120.png"/><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;">Since the thickness of the solder mask is not easy to control, it is also possible to use an approximate method based on the recommendations of the board manufacturer: subtract a specific value from the results calculated by the Surface model. It is recommended to subtract 8 ohms from the differential impedance and reduce the single-ended impedance. Go 2 ohms.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="margin-left:0.0000pt;mso-para-margin-left:0.0000gd;text-indent:0.0000pt;mso-char-indent-count:0.0000;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l0 level1 lfo1;"><span style="font-family:"font-size:18px;">4. </span><strong><span style="font-family:"font-size:18px;">PCB </span></strong><strong><span style="font-family:"font-size:18px;">R</span></strong><strong><span style="font-family:"font-size:18px;">equirements for </span></strong><strong><span style="font-family:"font-size:18px;">D</span></strong><strong><span style="font-family:"font-size:18px;">ifferential </span></strong><strong><span style="font-family:"font-size:18px;">P</span></strong><strong><span style="font-family:"font-size:18px;">air </span></strong><strong><span style="font-family:"font-size:18px;">T</span></strong><strong><span style="font-family:"font-size:18px;">races</span></strong> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l1 level1 lfo2;"><span style="font-family:"font-size:18px;">a. Determine the routing mode, parameters and impedance calculation. The differential pair traces are divided into an outer microstrip line differential mode and an inner stripline differential mode. By setting parameters reasonably, the impedance can be calculated by using an impedance calculation software (such as POLAR-SI9000) or an impedance calculation formula.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="margin-left:0.0000pt;mso-para-margin-left:0.0000gd;text-indent:0.0000pt;mso-char-indent-count:0.0000;text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;mso-list:l1 level1 lfo2;"><span style="font-family:"font-size:18px;">b. Take parallel equidistant lines. Determine the line width and spacing. When you are routing, you must strictly follow the calculated line width and spacing. The spacing between the two lines should remain the same, that is, keep parallel.</span> </p><p style="text-autospace:ideograph-numeric;mso-pagination:none;line-height:150%;"><span style="font-family:"font-size:18px;"> </span> </p><p style="line-height: 150%;"><span style="font-family:"font-size:18px;">There are two parallel ways: one for the two lines walking on the same side-by-side, and the other for the two lines walking over the top-by-side. Generally, the latter is used as the interlayer differential signal, because in the actual processing of the PCB, the alignment accuracy between the laminates is much lower than that of the same layer, and the dielectric loss during the lamination process cannot be Ensure that the spacing of the differential lines is equal to the thickness of the interlayer dielectric, which will cause differential impedance variations between the differential pairs between the layers. It is recommended to use the difference in the same layer as much as possible.</span> </p>
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